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Table of Contents

1 Fundamentals of Computer Design
1.1 Introduction 1
1.2 The Task of a Computer Designer 8
1.3 Technology Trends 11
1.4 Cost, Price and their Trends 14
1.5 Measuring and Reporting Performance 25
1.6 Quantitative Principles of Computer Design 40
1.7 Putting It All Together: Performance and Price-Performance 49
1.8 Another View: Power Consumption and Efficiency as the Metric 58
1.9 Fallacies and Pitfalls 59
1.10 Concluding Remarks 69
1.11 Historical Perspective and References 70
Exercises 77

2 Instruction Set Principles and Examples
2.1 Introduction 99
2.2 Classifying Instruction Set Architectures 101
2.3 Memory Addressing 105
2.4 Addressing Modes for Signal Processing 111
2.5 Type and Size of Operands 114
2.6 Operands for Media and Signal Processing 116
2.7 Operations in the Instruction Set 118
2.8 Operations for Media and Signal Processing 118
2.9 Instructions for Control Flow 122
2.10 Encoding an Instruction Set 127
2.11 Crosscutting Issues: The Role of Compilers 130
2.12 Putting It All Together: The MIPS Architecture 140
2.13 Another View: The Trimedia TM32 CPU 151
2.14 Fallacies and Pitfalls 152
2.15 Concluding Remarks 158
2.16 Historical Perspective and References 160
Exercises 172

3 Instruction-Level Parallelism and its Dynamic Exploitation
3.1 Instruction-Level Parallelism: Concepts and Challenges 221
3.2 Overcoming Data Hazards with Dynamic Scheduling 231
3.3 Dynamic Scheduling: Examples and the Algorithm 239
3.4 Reducing Branch Costs with Dynamic Hardware Prediction 247
3.5 High Performance Instruction Delivery 261
3.6 Taking Advantage of More ILP with Multiple Issue 268
3.7 Hardware-Based Speculation 278
3.8 Studies of the Limitations of ILP 294
3.9 Limitations on ILP for Realizable Processors 309
3.10 Putting It All Together: The P6 Microarchitecture 316
3.11 Another View: Thread Level Parallelism 329
3.12 Crosscutting Issues: Using an ILP Datapath to Exploit TLP 330
3.13 Fallacies and Pitfalls 330
3.14 Concluding Remarks 333
3.15 Historical Perspective and References 337

4 Exploiting Instruction Level Parallelism with Software Approaches
4.1 Basic Compiler Techniques for Exposing ILP 221
4.2 Static Branch Prediction 231
4.3 Static Multiple Issue: the VLIW Approach 234
4.4 Advanced Compiler Support for Exposing and Exploiting ILP 238
4.5 Hardware Support for Exposing More Parallelism at Compile-Time 260
4.6 Crosscutting Issues 270
4.7 Putting It All Together: The Intel IA-64 Architecture and Itanium Processor 271
4.8 Another View: ILP in the Embedded and Mobile Markets 283
4.9 Fallacies and Pitfalls 292
4.10 Concluding Remarks 293
4.11 Historical Perspective and References 295
Exercises 299

5 Memory-Hierarchy Design
5.1 Introduction 373
5.2 Review of the ABCs of Caches 376
5.3 Cache Performance 390
5.4 Reducing Cache Miss Penalty 398
5.5 Reducing Miss Rate 408
5.6 Reducing Cache Miss Penalty or Miss Rate via Parallelism 421
5.7 Reducing Hit Time 430
5.8 Main Memory and Organizations for Improving Performance 435
5.9 Memory Technology 442
5.10 Virtual Memory 448
5.11 Protection and Examples of Virtual Memory 457
5.12 Crosscutting Issues in the Design of Memory Hierarchies 467
5.13 Putting It All Together: Alpha 21264 Memory Hierarchy 471
5.14 Another View: The Emotion Engine of the Sony Playstation 2 479
5.15 Another View: The Sun Fire 6800 Server 483
5.16 Fallacies and Pitfalls 488
5.17 Concluding Remarks 495
5.18 Historical Perspective and References 498
Exercises 504

6 Multiprocessors and Thread-Level Parallelism
6.1 Introduction 635
6.2 Characteristics of Application Domains 649
6.3 Symmetric Shared-Memory Architectures 658
6.4 Performance of Symmetric Shared-Memory Multiprocessors 670
6.5 Distributed Shared-Memory Architectures 687
6.6 Performance of Distributed Shared-Memory Multiprocessors 697
6.7 Synchronization 705
6.8 Models of Memory Consistency: An Introduction 719
6.9 Multithreading: Exploiting Thread-Level Parallelism within a Processor 723
6.10 Crosscutting Issues 728
6.11 Putting It All Together: Sun's Wildfire Prototype 735
6.13 Another View: Embedded Multiprocessors 751
6.14 Fallacies and Pitfalls 752
6.15 Concluding Remarks 758
6.16 Historical Perspective and References 765
Exercises 780

7 Storage Systems
7.1 Introduction 485
7.2 Types of Storage Devices 487
7.3 Buses-Connecting I/O Devices to CPU/Memory 500
7.4 Reliability, Availability, and Dependability 509
7.5 RAID: Redundant Arrays of Inexpensive Disks 514
7.6 Errors and Failures in Real Systems 520
7.7 I/O Performance Measures 524
7.8 A Little Queuing Theory 530
7.9 Benchmarks of Storage Performance and Availability 541
7.10 Crosscutting Issues 547
7.11 Designing an I/O System in Five Easy Pieces 552
7.12 Putting It All Together: EMC Symmetrix and Celerra 565
7.13 Another View: Sanyo DSC-110 Digital Camera 572
7.14 Fallacies and Pitfalls 575
7.15 Concluding Remarks 581
7.16 Historical Perspective and References 582
Exercises 590

8 Interconnection Networks and Clusters
8.1 Introduction 563
8.2 A Simple Network 570
8.3 Interconnection Network Media 580
8.4 Connecting More Than Two Computers 583
8.5 Network Topology 592
8.6 Practical Issues for Commercial Interconnection Networks 600
8.7 Examples of Interconnection Networks 604
8.8 Internetworking 610
8.9 Crosscutting Issues for Interconnection Networks 615
8.10 Clusters 619
8.11 Designing a Cluster 624
8.12 Putting It All Together: The Goggle Cluster of PCs 638
8.13 Another View: Inside a Cell Phone 645
8.14 Fallacies and Pitfalls 650
8.15 Concluding Remarks 653
8.16 Historical Perspective and References 654
Exercises 660